A Hierarchical Timing Simulation Model

A hierarchical timing simulation model has been developed to deal with VLSI designs at any level of representation. A set of physically based parameters are used to characterize the behavior and timing of a semantic design object (cell) independent of its composition environment. As cells are composed, the parameters of the composite cell can be determined from those of the component cells either analytically or by simulation. Based on this model, a behavior-level simulator has been developed and combined with other tools to form an integrated design system that fully supports the structured design methodology

Signal Delay in General RC Networks with Application to Timing Simulation of Digital Integrated Circuits

Modeling digital MOS circuits by RC networks has become a well accepted practice for estimating delays. In 1981, Penfield and Rubinstein proposed a method to bound the waveforms of nodes in an RC tree network. In this paper, a single value of delay is derived for any node in a general RC network. The effects of parallel connections and stored charges are properly taken into consideration. The algorithms can be used either as a stand-alone simulator, or as a front end for producing initial waveforms for waveform-relaxation based circuit simulators. An experimental simulator called SDS (Signal Delay Simulator) has been developed. For all the examples tested so far, this simulator runs two to three orders of magnitude faster than SPICE, and detects all transitions and glitches at approximately the correct time

From Geometry to Logic

Transformation between five different intermediate forms used in VLSI design are discussed. The intermediate forms are: the D language, Akers' Diagrams, transistor listings, the sticks standard, and CIF language. They represent architecture, logic, transistor, topology and geometric levels respectively. To understand more about the relationships between these levels, a series of transformations from the CIF to the sticks standard, from the sticks standard to the transistor listing, and from the transistor listing to the Akers' Diagram are presented. By doing this, description gap between the logical world and the physical world is bridged. CAD developers often complain about the lack of a model that can be applied uniformly throughout the entire design process. Akers' diagrams seem to meet this demand. This work highlights this point. As an example, a shift register implemented in NMOS technology will appear many times in this thesis

A Hierarchical Timing Simulation Model for Digital Integrated Circuits and Systems

A hierarchical timing simulation model for digital MOS circuits and systems is presented. This model supports the structured design methodology, and can be applied to both "structure" and "behavior" representations of designs in a uniform manner. A simulator based on this model can run several orders of magnitude faster than any other simulators that offer the same amount of information. At the structure (transistor) level, the transient behavior of a digital MOS circuit is approximated by that of an RC network for estimating delays. The Penfield-Rubinstein RC tree model is extended to include the effects of parallel paths and initial charge distributions. As far as delay is concerned, a two-port RC network is characterized by three parameters: R: series resistance, C: loading capacitance and D: internal delay. These parameters can be determined hierarchically as networks are composed in various ways. The composition rules are derived directly from the Kirchoff's current and voltage laws, so that the consistency with physics is established. The (R, C, D) characterization of two-port RC networks is then generalized to describe the behavior of semantic cells at any level of representation. A semantic cell is a functional block which can be abstracted by its steady-state behavior to interface with other cells in the system. As semantic cells are composed, the parameters of the composite cell can be determined from those of the the component cells either analytically or by simulation. A Smalltalk implementation of the hierarchical timing simulation model is also presented

Signal Delay in General RC Networks

Based upon the delay of Elmore, a single value of delay is derived for any node in a general RC network. The effects of parallel connections and stored charge are properly taken into consideration. A technique called tree decomposition and load redistribution is introduced that is capable of dealing with general RC networks without sacrificing a number of desirable properties of tree networks. An experimental simulator called SDS (Signal Delay Simulator) has been developed. For all the examples tested so far, this simulator runs two to three orders of magnitude faster than SPICE, and detects all transitions and glitches at approximately the correct time

KINEMATICS ANALYSIS OF THE UPPER EXTREMITY DURING THE TWOHANDED BACKHAND DRIVE VOLLEY FOR FEMALE TENNIS PLAYERS

The purpose of this study was to discuss the motion characteristics of the arms in the two-handed backhand drive volley. Five elite female tennis players participated in this study, their two-handed backhand drive volley strokes were analysed, and all participants are right handed. Motion Analysis System with 10 Eagle Digital inferred high speed cameras at 200Hz were used for this study. The results show a similar elbow and wrist speed strategy in x-axis between two-handed ground stroke and drive volley, our study also found that the rear arm dominates the stroke and mainly provide the topspin that is required for the skill of the drive volley. In order to create better stroke efficiency, the right elbow reached peak velocity first, followed by the right wrist before racket impact with the ball

The Determinants of Corporate Credit Spreads in Taiwan

債券評價之結構模型已建立債券利率、股價波動度等變數在預測債券價格上的經濟理論基礎，而許多參考美國債券市場資料之文獻也發現股票和債券報酬率間具有密切關係，因此一些股票市場中的重要指標如股價淨值比和股價指數也能用以預測債券殖利率的變化，本研究欲探討這些重要變數與台灣公司債和公債間殖利率利差的關係。 我們擷取台灣債券交易市場的殖利率時間序列資料，利用向量自我迴歸模型及Johansen檢定發現這些變數與公司債和公債利差間具有共整合關係，且除了股價指數外皆能用以預測公司債與公債之利差。The structural models of corporate bonds have together established the theoretical basis on how interest rates and stock volatility can be used to explain the price of bonds. Many literatures that based on U.S. bond market have also found the strong connection between stock market and bond market returns. Some of the most commonly used indexes in stock market such as price-to-book ratio and the change of stock index can also help to predict the change of yield to maturity. We are trying to investigate the relationships between these variables and the yield spreads between corporate bonds and government bonds. Having taken the time series data from bond market in Taiwan, we found that there are cointegrations between yield spreads and those variables by using vector autoregression model and Johansen test. And except for stock index, these variables can be used to predict the yield spreads from different term-to-maturity

A VLSI Approach to Sound Synthesis

We present a VLSI approach to the generation of musical sounds. This approach allows the generation of very rich musical sounds using models that are easy to control and have parameters corresponding to physical attributes of musical instruments. Past efforts in musical sound generation have been plagued with several problems. The computational bandwidth that is needed to compute musical sounds is enormous, and it is hopeless to compute sounds in real time on a conventional general purpose computer. An even larger problem with previous efforts is the massive bandwidth needed for control and update of parameters. Sounds that come from physical sources are naturally represented by differential equations in time. Since there is a straight-forward correspondence between differential equations and finite difference equations, we can model musical instruments as simultaneous finite difference equations. Musical sounds can be produced by solving, in real time, the difference equations that model instruments. A natural architecture for solving finite difference equations is one with an interconnection matrix between processors that can be reconfigured or "programmed". A realization of a new instrument involves reconfiguring the connection matrix between the processing elements along with configuring connections to the outside world both for control and updates of parameters. For our basic unit of computation we have chosen a unit we call a UPE (Universal Processing Element) - it computes the function: A + BM + (1 - M)D We have implemented in nMOS technology a prototype systems of UPEs and have been successful in implementing some simple musical instruments on the system of UPEs